When it comes to electromagnetic interference, everyone will unanimously want to talk about wiring problems, problems caused by PCB circuit board materials, and surrounding environmental problems. Regarding the material of the circuit board, we cannot decide. My suggestion is to find a large manufacturer and make a request within the scope of funding. For the surrounding environment, a Faraday cage can be used for protection. Today, let's talk about PCB routing and board layer design to prevent electromagnetic interference.

When it comes to PCB circuit board routing and board layers, we will think of 2-layer boards and 4-layer boards. First introduce the microstrip line and stripline. A microstrip line is a PCB trace with a reference plane on only one side. We can also understand it as a trace in contact with air, that is, a trace on the top and bottom layers. Stripline refers to a transmission line with reference planes on both sides, which can be understood as the routing of the middle layer in a multilayer board.

Microstrip line for PCB can suppress RF, clock signal and high-speed data signal. We usually put it on the top layer for this reason. It is easy to introduce the RF signal of the external environment into the system using the microstrip line, which requires attention. The same strip line can better prevent RF radiation, but it can only be used for lower transmission speeds, but it can completely shield the RF of the internal wiring, because it has a better suppression of radio frequency radiation.

Usually experience tells us that the delay of microstrip line is small. For general FR4 board, the trace delay of 1inch microstrip line is about 140ps; the trace delay of stripline 1inch stripline is about 170ps; in addition, two You can use the tool sim9000 to calculate the characteristic impedance.

Special attention should be paid to signal transmission delay and crosstalk between circuits in the design of circuits. This is more obvious in high-speed circuit design, and impedance analyzers for impedance matching are even more important. If the impedance is not matched, the RF energy will be radiated or conduction (including crosstalk) from the internal wiring to change the surrounding electromagnetic environment and circuit characteristics.

When we are wiring, especially DDR2 or DDR3, we must control the length of the trace and the distance between the components. Too long will affect the effect and bring more troublesome debugging, but there is one advantage that the layout is not so Crowded, but the result can be overwhelming.

For the wiring of the processor chip (usually multi-layer circuit boards), the power layer should be divided at this time, and the power supply should be close to the cpu through vias and short and thick traces, and decoupling capacitors can effectively reduce noise . If the power layer is placed far away from the cpu during the design, the power trace length will be increased invisibly and the risk of noise generated by the cpu will affect the characteristics of the surrounding electrical appliances through the trace.

Nowadays, more and more high-performance and high-frequency CPUs are used. Because of their rich functions and the use of multi-layer boards for circuit design, the importance of the power layer has to be said. A good power plane segmentation can provide a low-impedance current return path, and this is the ultimate goal of our EMC design.

Regarding power splitting, it can generally be completed according to a three-step strategy: the first step is to set the power management rules as required; the second step is to divide the power layer according to the top-level component layout, and try to achieve one power management. element.

The third step is to use vias and traces to connect components. In this step, you need to pay attention to the routing rules mentioned above. In this way, the division of the power layer is realized.

When wiring, especially high-speed line signal wiring, we must keep the principles of 3W and 20H in mind. This can start to reduce electromagnetic interference in the first step.